1. Technical Field
The present invention relates to an electrostatic protection circuit that protects an internal circuit of a semiconductor integrated circuit device from ESD (electrostatic discharge). Furthermore, the invention relates to a semiconductor integrated circuit device that incorporates such an electrostatic protection circuit, and to an electronic device or the like that uses such a semiconductor integrated circuit device.
2. Related Art
Provision of an electrostatic protection circuit in a semiconductor integrated circuit device is carried out in order to prevent breakdown of an internal circuit due to static electricity charged on a person's body, a conveyance device or the like being applied to the internal circuit. For example, the electrostatic protection circuit is connected between a first terminal to which a power supply potential on a high potential side is supplied and a second terminal to which a power supply potential on a low potential side is supplied.
A positive charge is released to the second terminal via the electrostatic protection circuit when a positive charge is applied to the first terminal by electrostatic discharge or the like, thus enabling breakdown of the internal circuit to be prevented since an excessive voltage is not applied to the internal circuit. On the other hand, in order to avoid malfunction during normal operation, a trigger voltage and a hold voltage of the electrostatic protection circuit are desirably set higher than a power supply voltage.
As a related technology, an ESD protection circuit that is provided with a first clamp circuit and a second clamp circuit serially connected between a first power supply terminal and a second power supply terminal is disclosed in FIGS. 1 and 2 of JP-A-2014-120547. The first clamp circuit has a first protection transistor in which the drain is connected to a first high potential side node and the source and the gate are connected to a first low potential side node.
The second clamp circuit has a resistance element connected at one end to a second high potential side node, a capacitance element provided between a second low potential side node and the other end of the resistance element, an inverter that outputs a control signal of a logical value that depends on a potential of the connection point of the resistance element and the capacitance element, and a second protection transistor in which the drain is connected to the second high potential side node, the source is connected to the second low potential side node, and the control signal is supplied to the gate and the back gate.
Here, the resistance element, the capacitance element and the like that decide the response time of the second clamp circuit are also referred to as an RC timer. Although a high hold voltage can also be set by serially connecting the two clamp circuits having an RC timer, there is a risk of the trigger voltage falling below the power supply voltage due to the action of the RC timer, causing discharge current to flow during normal operation. According to the ESD protection circuit shown in FIGS. 1 and 2 of JP-A-2014-120547, the two clamp circuits are serially connected between the first power supply terminal and the second power supply terminal, making it possible to set a high hold voltage and to suppress an increase in discharge current during normal operation.
In the case where, however, the source-drain voltage of the first protection transistor shows a different value to the source-drain voltage of the second protection transistor immediately after power on, there is a risk of not being able to accuracy prevent breakdown of a protected circuit. Furthermore, a higher voltage than the voltage that is applied between the source and the drain of the first protection transistor is applied between the source and the drain of the second protection transistor, thus causing breakdown or deterioration of the second protection transistor to readily occur, due to prolonged normal operation.
In view of this, respectively connecting the first resistance element and the second resistance element that have the same resistance value in parallel to the first clamp circuit and the second clamp circuit has also been proposed, as shown in FIG. 9 of JP-A-2014-120547. The current that flows to the first resistance element is sufficiently larger than the leakage current that flows to the first clamp circuit, and the current that flows to the second resistance element is sufficiently larger than the leakage current that flows to the second clamp circuit. The source-drain voltage of the first protection transistor and the source-drain voltage of the second protection transistor are thereby equalized, enabling breakdown of a protected circuit to be accurately prevented, and breakdown or deterioration of the second protection transistor to be prevented.
JP-A-2014-120547 is an example of related art (see paras. 0005 to 0006, 0082 to 0086, FIGS. 1, 2 and 9).
As shown in FIG. 9 of JP-A-2014-120547, in the case of connecting the first resistance element and the second resistance element respectively in parallel to the first clamp circuit and the second clamp circuit in the ESD protection circuit, an increase in circuit area (chip size) will result. Also, in the case where a configuration is adopted in which the discharge operation starts immediately upon the voltage that is applied between the power supply terminals rising steeply, there is a possibility that all of the surge current produced by ESD immunity testing will flow into the electrostatic protection circuit incorporated in the semiconductor integrated circuit device.